- 容錯技術(shù)
- fault: n. 1.過失，過錯；罪過，責(zé)任。 2.缺點，缺陷，瑕疵 ...
- tolerant: adj. 1.忍受的；容忍的，原諒的，寬大的。 2.有耐 ...
- technique: n. 1.(專門)技術(shù)；(藝術(shù)上的)技巧，技能。 2.手 ...
- fault-tolerant technique: 容錯技術(shù)
- fault tolerant: 故障容限的; 容錯法
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fault tolerant technique中文什么意思
- 容錯技術(shù)
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例句與用法
- Based on distributed fault tolerant technique , high reliable bus technique of avionics and application technique of embedded real - time operation system , a design and an implementation of a distributed fault tolerant computer system which can control and manage aircraft onboard machine - electronic equipment integrated are presented
針對航空機電設(shè)備綜合控制管理預(yù)研項目，利用分布式容錯技術(shù)、高可靠航空電子總線技術(shù)和嵌入式實時多任務(wù)操作系統(tǒng)應(yīng)用技術(shù)，設(shè)計并實現(xiàn)了一個分布式容錯計算機系統(tǒng)。 - This paper mainly aims at the characteristics of the hardware and software structure of the parallel computer on satellite , and has fulfilled researches of fault tolerant technique in three aspects of control theories and engineering : the first research of the system level fault - tolerant module is based on the system structure of the parallel computer on satellite , a kind of cold backup module and a kind of hot backup module for multiprocessor computer have been put forward . then the research of software fault tolerant technique which is based on the operate system named rtems has been carried , the mission level fault - tolerate arithmetic and the system level fault - tolerate mechanism and strategies based on the check point technique have been put forward , at the same time the self - repair technique of software which has used the technique of system re - inject has been studied . finally the technique of components level fault - tolerant based on fpga has been studied , a kind of two level fault - tolerant project which aims at the fault - tolerant module of the parallel computer on satellite has been put forward , and the augmentative of circuit that project design realization need is little , this project can avoid any breakdown of any part logic circuit of the fpga
本課題主要針對星載并行計算機體系結(jié)構(gòu)及軟件結(jié)構(gòu)的特點,從如下三個方面進行了容錯控制理論研究和實踐工作:首先進行了基于星載多cpu并行計算機體系結(jié)構(gòu)的系統(tǒng)級容錯模型研究,提出了一種多cpu冷備份容錯模型和一種多cpu熱備份容錯模型;然后進行了基于rtems操作系統(tǒng)的軟件容錯技術(shù)研究,提出了任務(wù)級容錯調(diào)度算法以及基于檢查點技術(shù)的系統(tǒng)級容錯恢復(fù)機制和策略,同時研究了利用系統(tǒng)重注入進行軟件在線自修復(fù)的容錯技術(shù);最后研究了基于fpga的部件級容錯技術(shù),提出了對容錯模塊這一星載并行計算機關(guān)鍵部件的兩級容錯方案,實現(xiàn)該方案所需增加的電路少,可避免板級芯片以及fpga芯片內(nèi)部任何邏輯發(fā)生單點故障。